Compiling for SIMD Within a Register

Although SIMD (Single Instruction stream Multiple Data stream) parallel computers have existed for decades, it is only in the past few years that a new version of SIMD has evolved: SIMD Within A Register (SWAR). Unlike other styles of SIMD hardware, SWAR models are tuned to be integrated within conventional microprocessors, using their existing memory reference and instruction handling mechanisms, with the primar y goal of improving the speed of specific multimedia operations. Because the SWAR implementations for var ious microprocessors var y widely and each is missing instructions for some SWAR operations that are needed to support a more general, por table, high-level SIMD execution model, this paper focuses on how these missing operations can be implemented using either the existing SWAR hardware or even conventional 32-bit integer instructions. In addition, SWAR offers a few new challenges for compiler optimization; these issues are briefly introduced, as are the SWARC module language and the Scc compiler.